1. Field of the Invention
The present invention relates to, e.g., a MOS semiconductor device and a method of manufacturing the same and, more particularly, to a MOS semiconductor device having an improved source/drain region and to a method of manufacturing the same.
2. Background of the Invention
Recently, micropatterning and integration technologies for semiconductor devices are advancing. However, micropatterning of semiconductor devices is not based on scaling of a constant electric field, and the electric field in a semiconductor device tends to increase as the device is more finely micropatterned. Especially, in a MOS transistor, degradation in characteristics due to hot carriers is a serious problem.
As a preferable method of suppressing generation of hot carriers, a method of forming a source/drain having a so-called LDD structure is proposed, in which the first diffusion layer (LDD region) having a shallow junction and the second diffusion layer having a junction deeper than the first diffusion layer are made to partially overlap to form an impurity diffusion layer. According to the LDD structure, the concentration gradient at the drain end becomes gradual because of the relatively lightly doped LDD region, resulting in relaxation of field concentration. This decreases the substrate current, thereby suppressing generation of hot carriers.
The LDD region has a concentration for minimizing the substrate current at the drain end. This optimum concentration tends to gradually become high as the semiconductor device is more finely micropatterned. However, an increase in the concentration of the LDD region prompts the short channel effect, resulting in a decrease in threshold voltage or an increase in leakage current (punch through).
To suppress the short channel effect, the junction of the source/drain region may be made shallow. More specifically, the acceleration energy for ion-implanting impurities into the semiconductor substrate may be performed at a low temperature or for a short time. The shallow junction of the source/drain region also contributes to suppressing generation of hot carriers.
However, when the junction of the source/drain region is made shallow, the sheet resistance in this region increases, and the parasitic resistance also increases. The increase in parasitic resistance causes not only degradation in driving capability of the semiconductor device but also a decrease in operation margin of the semiconductor storage device (memory), resulting in degradation in characteristics.
To suppress the increase in parasitic resistance due to the shallow junction, a so-called raised source/drain structure is proposed (S. S. Wong et al., IEDM Technology Digest p. 634, 1984), in which the source/drain region is formed by raising it from the semiconductor substrate surface. A method using both the raised source drain structure and the LDD structure is also proposed (J. R. Pfiester et al., IEDM Technology Digest p. 885, 1992). Even in these methods, however, if annealing in device formation is the same as in the conventional method, the degree of thermal diffusion does not change, and the junction depth from the semiconductor substrate surface does not change either, so the above problem cannot be solved.
Japanese Patent Laid-Open No. 8-78671 discloses a method of implanting impurity ions through an ion implantation pad made of an insulating film or a conductive film to enable formation of a shallow junction by conventional annealing. In this method, dispersion due to ion scattering is increased so that the impurity distribution on the semiconductor substrate surface has a low peak and a large dispersion. However, in this method, the use of an insulating film as the ion implantation pad only enables to forming of a shallow junction and it cannot suppress the increase in parasitic resistance. When a conductive film is used as the ion implantation pad, the impurity concentration in the conductive film is lowered, so the sheet resistance of the conductive film cannot be sufficiently lowered. More specifically, when impurities are ion-implanted into the conductive film at a dose for sufficiently decreasing the sheet resistance, the impurities are diffused by subsequent annealing, so the shallow junction can hardly be formed.
Japanese Patent No. 2554055 discloses a method of implanting ions for forming a low-resistance polysilicon film. In this method, ion implantation is performed so that the impurity concentration is maximized immediately below the surface of the polysilicon film, and the polysilicon film does not become amorphous due to the impurities on the lowermost surface of the polysilicon film.
In fact, with ion implantation performed only once, the resistance of the polysilicon film can hardly be sufficiently lowered. Although this method contributes to reducing the contact resistance to the source/drain region, the effect for making the source/drain junction shallow is small.